66 search results - page 5 / 14 » On-Chip Inductance in X Architecture Enabled Design |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power densi...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
GLVLSI
2003
IEEE
14 years 29 days ago
2003
IEEE
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...
SIGGRAPH
2010
ACM
14 years 5 days ago
2010
ACM
The NVIDIA® OptiX™ ray tracing engine is a programmable system designed for NVIDIA GPUs and other highly parallel architectures. The OptiX engine builds on the key observation ...