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ASAP
2005
IEEE
182views Hardware» more  ASAP 2005»
14 years 1 months ago
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
Tom R. Jacobs, José L. Núñez-...
MSS
1999
IEEE
108views Hardware» more  MSS 1999»
13 years 12 months ago
Analysis of HPSS Performance Based on Per-file Transfer Logs
This paper analyses HPSS performance and, to a lesser extent, characterizes the SDSC HPSS workload, utilizing per-file transfer logs. The performance examined includes disk cache ...
Wayne Schroeder, Richard Marciano, Joe Lopez, Mich...
HPCA
2009
IEEE
14 years 8 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
COMSWARE
2007
IEEE
14 years 2 months ago
Leveraging MAC-layer information for single-hop wireless transport in the Cache and Forward Architecture of the Future Internet
— Cache and Forward (CNF) Architecture is a novel architecture aimed at delivering content efficiently to potentially large number of intermittently connected mobile hosts. It us...
Sumathi Gopal, Sanjoy Paul, Dipankar Raychaudhuri
SSDBM
1999
IEEE
113views Database» more  SSDBM 1999»
13 years 12 months ago
Multidimensional Indexing and Query Coordination for Tertiary Storage Management
In many scientific domains, experimental devices or simulation programs generate large volumes of data. The volumes of data may reach hundreds of terabytes and therefore it is imp...
Arie Shoshani, Luis M. Bernardo, Henrik Nordberg, ...