45 search results - page 8 / 9 » On-chip implementation of multiprocessor networks and switch... |
NETWORKING
2007
13 years 9 months ago
2007
Abstract. Parallel shared memory (PSM) routers represent an architectural approach for addressing the high memory bandwidth requirements dictated by output-queued switches. A funda...
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
HPCA
1996
IEEE
13 years 11 months ago
1996
IEEE
The current multiprocessors such asCray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and sw...
TPDS
2002
13 years 7 months ago
2002
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
LCN
2000
IEEE
13 years 12 months ago
2000
IEEE
Performance evaluation and reliability prediction are two important factors in the study of multiprocessor and cluster interconnects. One such interconnect is the Scalable Coheren...