261 search results - page 45 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
123
Voted
DFT
2008
IEEE
15 years 9 months ago
2008
IEEE
Integrated circuits (IC) targeting at the streaming applications for tomorrow are becoming a fast growing market. Applications such as beamforming require mass computing capabilit...
123
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ISPAN
2005
IEEE
15 years 8 months ago
2005
IEEE
Noncontiguous data access is a very common access pattern in many scientific applications. Using POSIX I/O to access many pieces of noncontiguous data segments will generate a lot...
129
Voted
DAC
2010
ACM
15 years 6 months ago
2010
ACM
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...
152
Voted
ACCV
2007
Springer
15 years 4 months ago
2007
Springer
Abstract. The trace quotient problem arises in many applications in pattern classification and computer vision, e.g., manifold learning, low-dimension embedding, etc. The task is ...
123
Voted
ICCD
2002
IEEE
15 years 11 months ago
2002
IEEE
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....