261 search results - page 45 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
DFT
2008
IEEE
14 years 2 months ago
2008
IEEE
Integrated circuits (IC) targeting at the streaming applications for tomorrow are becoming a fast growing market. Applications such as beamforming require mass computing capabilit...
ISPAN
2005
IEEE
14 years 1 months ago
2005
IEEE
Noncontiguous data access is a very common access pattern in many scientific applications. Using POSIX I/O to access many pieces of noncontiguous data segments will generate a lot...
DAC
2010
ACM
13 years 10 months ago
2010
ACM
Fault simulation is essential in test generation, design for test and reliability assessment of integrated circuits. Reliability analysis and the simulation of self-test structure...
ACCV
2007
Springer
13 years 9 months ago
2007
Springer
Abstract. The trace quotient problem arises in many applications in pattern classification and computer vision, e.g., manifold learning, low-dimension embedding, etc. The task is ...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....