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» Optimal Hardware Pattern Generation for Functional BIST
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TCAD
2008
110views more  TCAD 2008»
13 years 6 months ago
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC inte...
Shankar Mahadevan, Federico Angiolini, Jens Spars&...
ICDAR
2009
IEEE
13 years 5 months ago
Towards Handwritten Mathematical Expression Recognition
In this paper, we propose a new framework for online handwritten mathematical expression recognition. The proposed architecture aims at handling mathematical expression recognitio...
Ahmad-Montaser Awal, Harold Mouchère, Chris...
VLSISP
2008
173views more  VLSISP 2008»
13 years 7 months ago
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence...
Yedidya Hilewitz, Ruby B. Lee
BMCBI
2007
130views more  BMCBI 2007»
13 years 7 months ago
HMM-ModE - Improved classification using profile hidden Markov models by optimising the discrimination threshold and modifying e
Background: Profile Hidden Markov Models (HMM) are statistical representations of protein families derived from patterns of sequence conservation in multiple alignments and have b...
Prashant K. Srivastava, Dhwani K. Desai, Soumyadee...
GECCO
2010
Springer
173views Optimization» more  GECCO 2010»
14 years 9 days ago
Evolving the placement and density of neurons in the hyperneat substrate
The Hypercube-based NeuroEvolution of Augmenting Topologies (HyperNEAT) approach demonstrated that the pattern of weights across the connectivity of an artificial neural network ...
Sebastian Risi, Joel Lehman, Kenneth O. Stanley