261 search results - page 6 / 53 » Optimal Hardware Pattern Generation for Functional BIST |
ETS
2006
IEEE
14 years 1 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
DFT
2003
IEEE
14 years 24 days ago
2003
IEEE
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
TVLSI
2002
13 years 7 months ago
2002
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simp...
ITC
1996
IEEE
13 years 11 months ago
1996
IEEE
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...