Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a s...
David K. Tam, Reza Azimi, Livio Soares, Michael St...
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...
Creating robust real-time embedded software is critical in combining the physical world with computing, such as in consumer electronics or robotics. One challenge is the complexit...
Johannes Helander, Risto Serg, Margus Veanes, Prit...
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, ...