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» Optimal instruction scheduling using integer programming
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PLDI
2005
ACM
14 years 2 months ago
Register allocation for software pipelined multi-dimensional loops
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
Hongbo Rong, Alban Douillet, Guang R. Gao
CODES
2008
IEEE
14 years 3 months ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra
CADE
1998
Springer
14 years 24 days ago
System Description: card TAP: The First Theorem Prover on a Smart Card
Abstract. We present the first implementation of a theorem prover running on a smart card. The prover is written in Java and implements a dual tableau calculus. Due to the limited ...
Rajeev Goré, Joachim Posegga, Andrew Slater...
BMCBI
2008
211views more  BMCBI 2008»
13 years 8 months ago
CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment
Background: Searching for similarities in protein and DNA databases has become a routine procedure in Molecular Biology. The Smith-Waterman algorithm has been available for more t...
Svetlin Manavski, Giorgio Valle
ASPLOS
2011
ACM
13 years 5 days ago
Improving the performance of trace-based systems by false loop filtering
Trace-based compilation is a promising technique for language compilers and binary translators. It offers the potential to expand the compilation scopes that have traditionally be...
Hiroshige Hayashizaki, Peng Wu, Hiroshi Inoue, Mau...