378 search results - page 12 / 76 » Optimal integrated code generation for VLIW architectures |
EUROMICRO
2000
IEEE
14 years 24 days ago
2000
IEEE
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
IEEEINTERACT
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper introduces a method for improving program run-time performance by gathering work in an application and executing it efficiently in an integrated thread. Our methods ext...
HOTOS
1997
IEEE
14 years 18 days ago
1997
IEEE
We are building an operating system in which an integral run-time code generator constantly strives to improve the quality of already executing code. Our system is based on a plat...
ESTIMEDIA
2004
Springer
14 years 1 months ago
2004
Springer
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...