378 search results - page 4 / 76 » Optimal integrated code generation for VLIW architectures |
LCTRTS
2001
Springer
13 years 11 months ago
2001
Springer
Phase-decoupled methods for code generation are the state of the art in compilers for standard processors but generally produce code of poor quality for irregular target architect...
CF
2004
ACM
14 years 23 days ago
2004
ACM
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
ISCAS
2005
IEEE
14 years 28 days ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
ICCD
2000
IEEE
2000
IEEE
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures
13 years 11 months ago
This paper aims to provide a quantitative understanding of the performance of DSP and multimedia applications on very long instruction word (VLIW), single instruction multiple dat...