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HPCA
2009
IEEE
14 years 8 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
VLSID
2005
IEEE
167views VLSI» more  VLSID 2005»
14 years 8 months ago
A Methodology and Tooling Enabling Application Specific Processor Design
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
NOSSDAV
2009
Springer
14 years 2 months ago
Dynamic overlay multicast in 3D video collaborative systems
Multi-stream/multi-site 3D video collaborative systems are promising as they enable remote users to interact in a 3D virtual space with a sense of co-presence. However, the decent...
Wanmin Wu, Zhenyu Yang, Klara Nahrstedt
TITB
2002
172views more  TITB 2002»
13 years 7 months ago
Shape recovery algorithms using level sets in 2-D/3-D medical imagery: a state-of-the-art review
The class of geometric deformable models, also known as level sets, has brought tremendous impact to medical imagery due to its capability of topology preservation and fast shape r...
Jasjit S. Suri, Kecheng Liu, Sameer Singh, Swamy L...
DAC
2007
ACM
14 years 8 months ago
Placement of 3D ICs with Thermal and Interlayer Via Considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Brent Goplen, Sachin S. Sapatnekar