1291 search results - page 170 / 259 » Optimally switched linear systems |
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Data prefetching via helper threading has been extensively investigated on Simultaneous MultiThreading (SMT) or Virtual Multi-Threading (VMT) architectures. Although reportedly la...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
DSD
2003
IEEE
14 years 1 months ago
2003
IEEE
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
GLVLSI
1998
IEEE
14 years 4 days ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
IPPS
1998
IEEE
14 years 3 days ago
1998
IEEE
In this paper we extend a previously introduced method for optimizing the arbitration policy employed by ServerNet routers and we evaluate the method's effect on scalability....