Sciweavers

70 search results - page 8 / 14
» Optimization of combinational and sequential logic circuits ...
Sort
View
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Noise tolerant low voltage XOR-XNOR for fast arithmetic
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi
ICCD
1996
IEEE
104views Hardware» more  ICCD 1996»
14 years 21 days ago
Latch Redundancy Removal Without Global Reset
For circuits where there may be latches with no reset line, we show how to replace some of them with combinational logic. All previous work in sequential optimization by latch rem...
Shaz Qadeer, Robert K. Brayton, Vigyan Singhal
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
14 years 3 days ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 5 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
ICCD
2008
IEEE
165views Hardware» more  ICCD 2008»
14 years 5 months ago
Analysis and minimization of practical energy in 45nm subthreshold logic circuits
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...
David Bol, Renaud Ambroise, Denis Flandre, Jean-Di...