Sciweavers

468 search results - page 80 / 94
» Optimization of in-network data reduction
Sort
View
HPCA
2000
IEEE
14 years 2 months ago
Register Organization for Media Processing
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
Scott Rixner, William J. Dally, Brucek Khailany, P...
IEEEPACT
2000
IEEE
14 years 2 months ago
Exploring the Limits of Sub-Word Level Parallelism
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
Kevin Scott, Jack W. Davidson
IPPS
1997
IEEE
14 years 2 months ago
Enhancing Software DSM for Compiler-Parallelized Applications
Current parallelizing compilers for message-passing machines only support a limited class of data-parallel applications. One method for eliminating this restriction is to combine ...
Peter J. Keleher, Chau-Wen Tseng
ASPDAC
2008
ACM
130views Hardware» more  ASPDAC 2008»
13 years 12 months ago
Architecture-level thermal behavioral characterization for multi-core microprocessors
In this paper, we investigate a new architecture-level thermal characterization problem from behavioral modeling perspective to address the emerging thermal related analysis and o...
Duo Li, Sheldon X.-D. Tan, Murli Tirumala
NIPS
2008
13 years 11 months ago
Multi-Level Active Prediction of Useful Image Annotations for Recognition
We introduce a framework for actively learning visual categories from a mixture of weakly and strongly labeled image examples. We propose to allow the categorylearner to strategic...
Sudheendra Vijayanarasimhan, Kristen Grauman