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» Optimizing Compilation of CLP(R)
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DAC
2005
ACM
13 years 9 months ago
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
Ho Young Kim, Tag Gon Kim
FPL
2008
Springer
143views Hardware» more  FPL 2008»
13 years 9 months ago
Fast toggle rate computation for FPGA circuits
This paper presents a fast and scalable method of computing signal toggle rate in FPGA-based circuits. Our technique is a vectorless estimation technique, which can be used in a C...
Tomasz S. Czajkowski, Stephen Dean Brown
LREC
2010
136views Education» more  LREC 2010»
13 years 8 months ago
LoonyBin: Keeping Language Technologists Sane through Automated Management of Experimental (Hyper)Workflows
Many contemporary language technology systems are characterized by long pipelines of tools with complex dependencies. Too often, these workflows are implemented by ad hoc scripts;...
Jonathan H. Clark, Alon Lavie
LREC
2008
75views Education» more  LREC 2008»
13 years 8 months ago
Selection of Japanese-English Equivalents by Integrating High-quality Corpora and Huge Amounts of Web Data
As a first step to developing systems that enable non-native speakers to output near-perfect English sentences for given mixed EnglishJapanese sentences, we propose new approaches...
Qing Ma, Koichi Nakao, Masaki Murata, Hitoshi Isah...
IJCAI
2007
13 years 8 months ago
A Heuristic Search Approach to Planning with Temporally Extended Preferences
In this paper we propose a suite of techniques for planning with temporally extended preferences (TEPs). To this end, we propose a method for compiling TEP planning problems into ...
Jorge A. Baier, Fahiem Bacchus, Sheila A. McIlrait...