244 search results - page 13 / 49 » Optimizing Loop Performance for Clustered VLIW Architectures |
EMSOFT
2004
Springer
14 years 1 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
We present the TM3270 media-processor, the latest TriMedia VLIW processor, tuned to address the performance demands of standard definition video processing, combined with embedded...
IEEECIT
2010
IEEE
13 years 6 months ago
2010
IEEE
- The increase of embedded applications complexity has demanded hardware more flexible while providing higher performance. Reconfigurable architectures and stream processing have b...
SAMOS
2004
Springer
14 years 1 months ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
CLUSTER
2004
IEEE
13 years 11 months ago
2004
IEEE
Improving memory performance at software level is more effective in reducing the rapidly expanding gap between processor and memory performance. Loop transformations (e.g. loop un...