363 search results - page 60 / 73 » Optimizing Memory Accesses For Spatial Computation |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--The growing complexity in computer system hierarchies due to the increase in the number of cores per processor, levels of cache (some of them shared) and the number of pr...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
Previous studies have shown that array regrouping and structure splitting significantly improve data locality. The most effective technique relies on profiling every access to eve...
PLDI
1999
ACM
13 years 12 months ago
1999
ACM
Load-reuse analysis finds instructions that repeatedly access the same memory location. This location can be promoted to a register, eliminating redundant loads by reusing the re...