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» Optimizing Memory Accesses For Spatial Computation
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ICPP
2008
IEEE
14 years 2 months ago
VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a Field-Programmable-Gate-Array (FPGA) based prototype we show a latency...
Heiner Litz, Holger Fröning, Mondrian Nü...
CCGRID
2009
IEEE
14 years 2 months ago
Improving Parallel Write by Node-Level Request Scheduling
In a cluster of multiple processors or cpu-cores, many processes may run on each compute node. Each process tends to issue contiguous I/O requests for snapshot, checkpointing or s...
Kazuki Ohta, Hiroya Matsuba, Yutaka Ishikawa
ICDT
2001
ACM
147views Database» more  ICDT 2001»
14 years 3 days ago
Parallelizing the Data Cube
This paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one f...
Frank K. H. A. Dehne, Todd Eavis, Susanne E. Hambr...
IPPS
2009
IEEE
14 years 2 months ago
Implementing and evaluating multithreaded triad census algorithms on the Cray XMT
Commonly represented as directed graphs, social networks depict relationships and behaviors among social entities such as people, groups, and organizations. Social network analysi...
George Chin Jr., Andrès Márquez, Sut...
IWOMP
2007
Springer
14 years 1 months ago
Supporting OpenMP on Cell
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Ton...