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ISHPC
2000
Springer
13 years 11 months ago
Loop Termination Prediction
Deeply pipelined high performance processors require highly accurate branch prediction to drive their instruction fetch. However there remains a class of events which are not easi...
Timothy Sherwood, Brad Calder
PLDI
2000
ACM
13 years 11 months ago
Exploiting superword level parallelism with multimedia instruction sets
Increasing focus on multimedia applications has prompted the addition of multimedia extensions to most existing general purpose microprocessors. This added functionality comes pri...
Samuel Larsen, Saman P. Amarasinghe
ICPADS
2006
IEEE
14 years 1 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
CGO
2007
IEEE
14 years 1 months ago
Loop Optimization using Hierarchical Compilation and Kernel Decomposition
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...
Denis Barthou, Sébastien Donadio, Patrick C...
BTW
2003
Springer
170views Database» more  BTW 2003»
14 years 21 days ago
Executing Nested Queries
Abstract: Optimization of nested queries, in particular finding equivalent “flattened” queries for queries that employ the SQL sub-query construct, has been researched extensiv...
Goetz Graefe