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ICS
2009
Tsinghua U.
14 years 3 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
IEEEPACT
2002
IEEE
14 years 1 months ago
Increasing and Detecting Memory Address Congruence
A static memory reference exhibits a unique property when its dynamic memory addresses are congruent with respect to some non-trivial modulus. Extraction of this congruence inform...
Samuel Larsen, Emmett Witchel, Saman P. Amarasingh...
WWW
2006
ACM
14 years 9 months ago
XML screamer: an integrated approach to high performance XML parsing, validation and deserialization
This paper describes an experimental system in which customized high performance XML parsers are prepared using parser generation and compilation techniques. Parsing is integrated...
Margaret Gaitatzes Kostoulas, Morris Matsa, Noah M...
SAS
2010
Springer
262views Formal Methods» more  SAS 2010»
13 years 7 months ago
Concurrent Separation Logic for Pipelined Parallelization
Recent innovations in automatic parallelizing compilers are showing impressive speedups on multicore processors using shared memory with asynchronous channels. We have formulated a...
Christian J. Bell, Andrew W. Appel, David Walker
JSS
2007
120views more  JSS 2007»
13 years 8 months ago
The design and evaluation of path matching schemes on compressed control flow traces
A control flow trace captures the complete sequence of dynamically executed basic blocks and function calls. It is usually of very large size and therefore commonly stored in com...
Yongjing Lin, Youtao Zhang, Rajiv Gupta