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GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
14 years 3 months ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar
SIGIR
2006
ACM
14 years 3 months ago
Hybrid index maintenance for growing text collections
We present a new family of hybrid index maintenance strategies to be used in on-line index construction for monotonically growing text collections. These new strategies improve up...
Stefan Büttcher, Charles L. A. Clarke, Brad L...
CODES
2005
IEEE
14 years 2 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
WMPI
2004
ACM
14 years 2 months ago
A compressed memory hierarchy using an indirect index cache
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
Erik G. Hallnor, Steven K. Reinhardt
IPSN
2004
Springer
14 years 2 months ago
The impact of spatial correlation on routing with compression in wireless sensor networks
The efficacy of data aggregation in sensor networks is a function of the degree of spatial correlation in the sensed phenomenon. While several data aggregation (i.e., routing with...
Sundeep Pattem, Bhaskar Krishnamachari, Ramesh Gov...