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JUCS
2000
120views more  JUCS 2000»
13 years 9 months ago
Compiler Generated Multithreading to Alleviate Memory Latency
: Since the era of vector and pipelined computing, the computational speed is limited by the memory access time. Faster caches and more cache levels are used to bridge the growing ...
Kristof Beyls, Erik H. D'Hollander
VEE
2009
ACM
171views Virtualization» more  VEE 2009»
14 years 4 months ago
Dynamic memory balancing for virtual machines
Virtualization essentially enables multiple operating systems and applications to run on one physical computer by multiplexing hardware resources. A key motivation for applying vi...
Weiming Zhao, Zhenlin Wang
TVLSI
2008
89views more  TVLSI 2008»
13 years 10 months ago
Test Set Development for Cache Memory in Modern Microprocessors
Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transis...
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Sta...
ICTAI
2010
IEEE
13 years 8 months ago
Metropolis Particle Swarm Optimization Algorithm with Mutation Operator for Global Optimization Problems
When a local optimal solution is reached with classical Particle Swarm Optimization (PSO), all particles in the swarm gather around it, and escaping from this local optima becomes...
Lhassane Idoumghar, M. Idrissi-Aouad, Mahmoud Melk...
ASPDAC
2001
ACM
117views Hardware» more  ASPDAC 2001»
14 years 1 months ago
Low power techniques for address encoding and memory allocation
- This paper presents encoding techniques to optimize the switching activity on a multiplexed DRAM address bus. The DRAM switching activity can be classified either as external (be...
Wei-Chung Cheng, Massoud Pedram