2703 search results - page 168 / 541 » Optimizing memory transactions |
PE
2002
Springer
13 years 9 months ago
2002
Springer
The study presented in this paper is motivated by the performance analysis of response times in distributed information systems, where transactions are handled by iterative server...
IPPS
2007
IEEE
14 years 4 months ago
2007
IEEE
In distributed hybrid computing systems, traditional sequential processors are loosely coupled with reconfigurable hardware for optimal performance. This loose coupling proves to...
IPPS
2007
IEEE
14 years 4 months ago
2007
IEEE
In this paper, we present a mechanism for automatic management of the memory hierarchy, including secondary storage, in the context of a global address space parallel programming ...
ATS
2005
IEEE
14 years 3 months ago
2005
IEEE
Abstract: Fabrication process improvements and technology scaling results in modifications in the characteristics and in the behavior of manufactured memory chips, which also modi...
WISA
2004
Springer
14 years 3 months ago
2004
Springer
In implementing cryptographic algorithms on limited devices such as smart cards, speed and memory optimization had always been a challenge. With the advent of side channel attacks,...