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TJS
2008
95views more  TJS 2008»
13 years 10 months ago
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Akshat Verma, Sandeep Sen
POPL
2009
ACM
14 years 10 months ago
Relaxed memory models: an operational approach
Memory models define an interface between programs written in some language and their implementation, determining which behaviour the memory (and thus a program) is allowed to hav...
Gérard Boudol, Gustavo Petri
STOC
2004
ACM
129views Algorithms» more  STOC 2004»
14 years 10 months ago
Sorting and searching in the presence of memory faults (without redundancy)
We investigate the design of algorithms resilient to memory faults, i.e., algorithms that, despite the corruption of some memory values during their execution, are able to produce...
Irene Finocchi, Giuseppe F. Italiano
ICCAD
2007
IEEE
123views Hardware» more  ICCAD 2007»
14 years 7 months ago
Mapping model with inter-array memory sharing for multidimensional signal processing
Abstract – The storage requirements in data-intensive signal processing systems (including applications in video and image processing, artificial vision, medical imaging, real-t...
Ilie I. Luican, Hongwei Zhu, Florin Balasa
ISCA
2009
IEEE
138views Hardware» more  ISCA 2009»
14 years 4 months ago
Achieving predictable performance through better memory controller placement in many-core CMPs
In the near term, Moore’s law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents th...
Dennis Abts, Natalie D. Enright Jerger, John Kim, ...