Sciweavers

2703 search results - page 48 / 541
» Optimizing memory transactions
Sort
View
VMCAI
2009
Springer
14 years 3 months ago
An Abort-Aware Model of Transactional Programming
There has been a lot of recent research on transaction-based concurrent programming, aimed at offering an easier concurrent programming paradigm that enables programmers to better...
Kousha Etessami, Patrice Godefroid
SAC
2009
ACM
14 years 3 months ago
Response time analysis of software transactional memory-based distributed real-time systems
We consider distributed real-time systems where concurrency control is managed using software transactional memory. For such a method we propose an algorithm to compute an upper b...
Sherif Fadel Fahmy, Binoy Ravindran, E. Douglas Je...
FPGA
2012
ACM
285views FPGA» more  FPGA 2012»
12 years 4 months ago
Optimizing SDRAM bandwidth for custom FPGA loop accelerators
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order in which address...
Samuel Bayliss, George A. Constantinides
SYSTOR
2009
ACM
14 years 3 months ago
Transactifying Apache's cache module
Apache is a large-scale industrial multi-process and multithreaded application, which uses lock-based synchronization. We report on our experience in modifying Apache’s cache mo...
Haggai Eran, Ohad Lutzky, Zvika Guz, Idit Keidar
DAC
2012
ACM
11 years 11 months ago
STM concurrency control for embedded real-time software with tighter time bounds
We consider software transactional memory (STM) concurrency control for multicore real-time software, and present a novel contention manager (CM) for resolving transactional conï¬...
Mohammed El-Shambakey, Binoy Ravindran