2048 search results - page 231 / 410 » Optimizing pipelines for power and performance |
ACSAC
2000
IEEE
14 years 20 days ago
2000
IEEE
The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder The...
IPPS
2000
IEEE
14 years 19 days ago
2000
IEEE
The primary goal of the Multimedia Router (MMR) project is the design and implementation of a router optimized for multimedia applications. The router is targeted for use in clust...
AGENTS
2000
Springer
14 years 18 days ago
2000
Springer
Recent research has made it possible to build information agents that retrieve and integrate information from the World Wide Web. Although there now exist solutions for modeling W...
RTAS
1998
IEEE
14 years 14 days ago
1998
IEEE
Static timing analyzers need to know the minimum and maximum number of iterations associated with each loop in a real-time program so accurate timing predictions can be obtained. ...
CGF
2010
13 years 8 months ago
2010
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...