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» Optimizing pipelines for power and performance
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NOCS
2008
IEEE
14 years 2 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
CGF
2008
125views more  CGF 2008»
13 years 8 months ago
Interactive Visualization for Memory Reference Traces
We present the Memory Trace Visualizer (MTV), a tool that provides interactive visualization and analysis of the sequence of memory operations performed by a program as it runs. A...
A. N. M. Imroz Choudhury, Kristin C. Potter, Steve...
CORR
2008
Springer
147views Education» more  CORR 2008»
13 years 8 months ago
Impact of CSI on Distributed Space-Time Coding in Wireless Relay Networks
We consider a two-hop wireless network where a transmitter communicates with a receiver via M relays with an amplify-and-forward (AF) protocol. Recent works have shown that sophis...
Mari Kobayashi, Xavier Mestre
DCC
2007
IEEE
14 years 7 months ago
Transmission Over Slowly Fading Channels Using Unreliable Quantized Feedback
We study the problem of maximizing the expected rate over a slowly fading channel with quantized channel state information at the transmitter (CSIT). This problem has been recentl...
Siavash Ekbatani, Farzad Etemadi, Hamid Jafarkhani
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 2 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian