867 search results - page 34 / 174 » Optimizing synthesis with metasketches |
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
FCCM
2002
IEEE
14 years 2 months ago
2002
IEEE
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
CCE
2004
13 years 9 months ago
2004
: This paper describes the implementation of a meta-heuristic optimization approach, Tabu Search (TS), for Heat Exchanger Networks (HEN) synthesis and compares this approach to oth...
DATE
2000
IEEE
14 years 2 months ago
2000
IEEE
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...