867 search results - page 5 / 174 » Optimizing synthesis with metasketches |
RSP
1999
IEEE
14 years 1 months ago
1999
IEEE
SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The ...
DATE
2010
IEEE
14 years 2 months ago
2010
IEEE
Abstract—Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checki...
GECCO
2006
Springer
14 years 1 months ago
2006
Springer
DAC
2006
ACM
14 years 10 months ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
DAC
1994
ACM
14 years 1 months ago
1994
ACM
This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is ...