620 search results - page 26 / 124 » Optimizing the BSD routing system for parallel processing |
FPL
2009
Springer
14 years 5 days ago
2009
Springer
Networks-on-Chips (NoCs) are an emerging communication topology paradigm in single chip VLSI design, enhancing parallelism and system scalability. Processing units (PUs) connect t...
INFOCOM
2011
IEEE
12 years 11 months ago
2011
IEEE
Abstract—Large-scale data processing needs of enterprises today are primarily met with distributed and parallel computing in data centers. MapReduce has emerged as an important p...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
In this work we present a system for implementing the placement and routing stages in the FPGA cycle of design, into the physical design stage. We start with the ISCAS benchmarks,...
IPPS
2003
IEEE
14 years 25 days ago
2003
IEEE
In this paper, we describe a compilation system that automates much of the process of performance tuning that is currently done manually by application programmers interested in h...
WSC
2008
13 years 10 months ago
2008
Optimization and design of production and service operations has been a cornerstone of simulation applications for many years. Recently there has been increasing interest in excel...