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PATMOS
2007
Springer
14 years 2 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
TCAD
2008
172views more  TCAD 2008»
13 years 8 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
14 years 2 days ago
Timing optimization by bit-level arithmetic transformations
This paper describes a method to optimize the performance of data paths. It is based on bit-level arithmetic transformations, and is especially suited to optimize large adder stru...
Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De M...
CIVR
2009
Springer
174views Image Analysis» more  CIVR 2009»
14 years 3 months ago
Evaluation of GIST descriptors for web-scale image search
The GIST descriptor has recently received increasing attention in the context of scene recognition. In this paper we evaluate the search accuracy and complexity of the global GIST...
Matthijs Douze, Herve Jegou, Harsimrat Sandhawalia...
CSCLP
2003
Springer
14 years 1 months ago
Experimental Evaluation of Interchangeability in Soft CSPs
Abstract. In [8], Freuder defined interchangeability for classical Constraint Satisfaction Problems (CSPs). Recently [2], we extended the definition of interchangeability to Soft ...
Nicoleta Neagu, Stefano Bistarelli, Boi Faltings