1990 search results - page 24 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
ASPLOS
1989
ACM
13 years 11 months ago
1989
ACM
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...
ICS
1999
Tsinghua U.
13 years 12 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
EH
2004
IEEE
13 years 11 months ago
2004
IEEE
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
CC
2003
Springer
14 years 24 days ago
2003
Springer
Cache memories were invented to decouple fast processors from slow memories. However, this decoupling is only partial, and many researchers have attempted to improve cache use by p...