1990 search results - page 28 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
ACMMSP
2004
ACM
14 years 1 months ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
As multi-core architectures flourish in the marketplace, multi-application workload scenarios (such as server consolidation) are growing rapidly. When running multiple application...
EUROPAR
1999
Springer
13 years 12 months ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
ICPP
1999
IEEE
13 years 12 months ago
1999
IEEE
Instruction fetch bandwidth is feared to be a major limiting factor to the performance of future wide-issue aggressive superscalars. In this paper, we focus on Database applicatio...
VLDB
2005
ACM
14 years 1 months ago
2005
ACM
Simultaneous multithreading (SMT) allows multiple threads to supply instructions to the instruction pipeline of a superscalar processor. Because threads share processor resources,...