Sciweavers

1990 search results - page 316 / 398
» Optimizing the Instruction Cache Performance of the Operatin...
Sort
View
BCS
2008
13 years 10 months ago
A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming
This paper describes a customisable processor designed to accelerate execution of inductive logic programming, targeting advanced field-programmable gate array (FPGA) technology. ...
Andreas Fidjeland, Wayne Luk, Stephen Muggleton
ASPLOS
2012
ACM
12 years 4 months ago
Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults
Future microprocessors need low-cost solutions for reliable operation in the presence of failure-prone devices. A promising approach is to detect hardware faults by deploying low-...
Siva Kumar Sastry Hari, Sarita V. Adve, Helia Naei...
USENIX
2001
13 years 10 months ago
Flexible Control of Parallelism in a Multiprocessor PC Router
SMP Click is a software router that provides both flexibility and high performance on stock multiprocessor PC hardware. It achieves high performance using device, buffer, and queu...
Benjie Chen, Robert Morris
CC
2008
Springer
172views System Software» more  CC 2008»
13 years 11 months ago
Efficient Context-Sensitive Shape Analysis with Graph Based Heap Models
The performance of heap analysis techniques has a significant impact on their utility in an optimizing compiler. Most shape analysis techniques perform interprocedural dataflow ana...
Mark Marron, Manuel V. Hermenegildo, Deepak Kapur,...
ACMACE
2009
ACM
14 years 7 days ago
Enhancing a motion capture interface by introducing context management
Nowadays, video games propose rich scenarios with movementsbased game play, through the manipulation of dedicated devices. The motivation of this study is the elaboration of a com...
Francois Picard, Pascal Estraillier