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ECRTS
2007
IEEE
14 years 2 months ago
Cache-Aware Timing Analysis of Streaming Applications
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
Samarjit Chakraborty, Tulika Mitra, Abhik Roychoud...
EURODAC
1995
IEEE
195views VHDL» more  EURODAC 1995»
13 years 11 months ago
A hardware/software partitioning algorithm for pipelined instruction set processor
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this...
Binh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi
LCTRTS
2005
Springer
14 years 1 months ago
A sample-based cache mapping scheme
Applications running on the StrongARM SA-1110 or XScale processor cores can specify cache mapping for each virtual page to achieve better cache utilization. In this work, we descr...
Rong Xu, Zhiyuan Li
TOCS
1998
209views more  TOCS 1998»
13 years 7 months ago
UFO: A Personal Global File System Based on User-Level Extensions to the Operating System
ile system abstractions, they all require either changes to the operating system or modifications to standard libraries. The article gives a detailed performance analysis of our ap...
Albert Alexandrov, Maximilian Ibel, Klaus E. Schau...
EUROPAR
2001
Springer
14 years 4 days ago
Load Redundancy Elimination on Executable Code
Optimizations performed at link time or directly applied to nal program executables have received increased attention in recent years. This paper discuss the discovery and elimina...
Manel Fernández, Roger Espasa, Saumya K. De...