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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
LKR
2008
13 years 9 months ago
Design and Prototype of a Large-Scale and Fully Sense-Tagged Corpus
Sense tagged corpus plays a very crucial role to Natural Language Processing, especially on the research of word sense disambiguation and natural language understanding. Having a l...
Sue-jin Ker, Chu-Ren Huang, Jia-Fei Hong, Shi-Yin ...
ICCAD
1995
IEEE
108views Hardware» more  ICCAD 1995»
13 years 11 months ago
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
This paper presents a linear time algorithm to reduce a large RC interconnect network into subnetworks which are approximated with lower order equivalent RC circuits. The number o...
Haifang Liao, Wayne Wei-Ming Dai
COMCOM
2006
168views more  COMCOM 2006»
13 years 7 months ago
Relay node placement in large scale wireless sensor networks
Scalability and extended lifetime are two critical design goals of any large scale wireless sensor network. A two-tiered network model has been proposed recently for this purpose....
Jian Tang, Bin Hao, Arunabha Sen
ICML
2010
IEEE
13 years 8 months ago
Large Scale Max-Margin Multi-Label Classification with Priors
We propose a max-margin formulation for the multi-label classification problem where the goal is to tag a data point with a set of pre-specified labels. Given a set of L labels, a...
Bharath Hariharan, Lihi Zelnik-Manor, S. V. N. Vis...