Explicit Data Graph Execution (EDGE) architectures offer the possibility of high instruction-level parallelism with energy efficiency. In EDGE architectures, the compiler breaks ...
Aaron Smith, Jon Gibson, Bertrand A. Maher, Nichol...
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Abstract— This paper considers jointly optimal design of crosslayer congestion control, routing and scheduling for ad hoc wireless networks. We first formulate the rate constrai...
Lijun Chen, Steven H. Low, Mung Chiang, John C. Do...
— This paper presents a two-level strategy for topology control in wireless sensor networks. The energy saving methods in most of the existing research work can be categorized in...
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...