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» Parallel Computation of the SVD of a Matrix Product
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ISCAS
2003
IEEE
105views Hardware» more  ISCAS 2003»
14 years 22 days ago
Algorithmic partial analog-to-digital conversion in mixed-signal array processors
We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processor...
Roman Genov, Gert Cauwenberghs
IPPS
1999
IEEE
13 years 11 months ago
Large Scale Simulation of Particulate Flows
Simulations of particles in fluid flows are of great interest to numerous industries using sedimentation, fluidization, lubricated transport, and hydraulic fracturing of hydrocarb...
Ahmed H. Sameh, Vivek Sarin
IPPS
2002
IEEE
14 years 11 days ago
Fast Inductance Extraction of Large VLSI Circuits
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
Hemant Mahawar, Vivek Sarin, Weiping Shi
HPCN
1997
Springer
13 years 11 months ago
A Programming Interface for NUMA Shared-Memory Clusters
Abstract. We describe a programming interface for parallel computing on NUMA (NonUniform Memory Access) shared memory machines. Although the interest in this architecture is rapidl...
Marcus Dormanns, Walter Sprangers, Hubert Ertl, Th...
ASPLOS
2009
ACM
14 years 8 months ago
QR decomposition on GPUs
QR decomposition is a computationally intensive linear algebra operation that factors a matrix A into the product of a unitary matrix Q and upper triangular matrix R. Adaptive sys...
Andrew Kerr, Dan Campbell, Mark Richards