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IPPS
1994
IEEE
13 years 12 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
ICPP
2000
IEEE
14 years 4 days ago
Issues in Designing and Implementing a Scalable Virtual Interface Architecture
The Virtual Interface Architecture brings the benefits of low latency User-level Networking to a cluster environment. With an increasing number of communication channels created ...
Shailabh Nagar, Anand Sivasubramaniam, Jorge Rodri...
WIA
2000
Springer
13 years 11 months ago
Fast Implementations of Automata Computations
Abstract. In 6], G. Myers describes a bit-vector algorithm to compute the edit distance between strings. The algorithm converts an input sequence to an output sequence in a paralle...
Anne Bergeron, Sylvie Hamel
SPAA
2009
ACM
14 years 8 months ago
A lightweight in-place implementation for software thread-level speculation
Thread-level speculation (TLS) is a technique that allows parts of a sequential program to be executed in parallel. TLS ensures the parallel program's behaviour remains true ...
Cosmin E. Oancea, Alan Mycroft, Tim Harris
IJON
2000
69views more  IJON 2000»
13 years 7 months ago
PARALLEL NEUROSYS: A system for the simulation of very large networks of biologically accurate neurons on parallel computers
We present a software package for the simulation of very large neuronal networks on parallel computers. The package can be run on any system with an implementation of the Message ...
Peter Pacheco, Marcelo Camperi, Toshi Uchino