5553 search results - page 1110 / 1111 » Parallel Implementation of Sch |
DSN
2011
IEEE
12 years 7 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
The L2 cache is commonly managed using LRU policy. For workloads that have a working set larger than L2 cache, LRU behaves poorly, resulting in a great number of less reused lines...
EUROSYS
2010
ACM
14 years 1 months ago
2010
ACM
The deluge of huge data sets such as those provided by
sensor networks, online transactions, and the web provide
exciting opportunities for data analysis. The scale of the
data ...
EUROPAR
2004
Springer
14 years 1 months ago
2004
Springer
The interesting properties of P2P systems (high availability despite peer volatility, support for heterogeneous architectures, high scalability, etc.) make them attractive for dist...
3DIC
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract— Networks-on-chip (NoC) is emerging as a key onchip communication architecture for multiprocessor systemson-chip (MPSoC). In traditional electronic NoCs, high bandwidth ...