309 search results - page 24 / 62 » Parallel Memory Architecture for Arbitrary Stride Accesses |
JUCS
2000
13 years 7 months ago
2000
: Since the era of vector and pipelined computing, the computational speed is limited by the memory access time. Faster caches and more cache levels are used to bridge the growing ...
ICCD
1999
IEEE
13 years 12 months ago
1999
IEEE
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
This work deals with the scheduling problem of a directed acyclic graph with interprocessor communication delays. The objective is to minimize the makespan, taking into account the...
ASPLOS
2009
ACM
14 years 8 months ago
2009
ACM
Current shared memory multicore and multiprocessor systems are nondeterministic. Each time these systems execute a multithreaded application, even if supplied with the same input,...