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» Parallel Processing Architectures for Reconfigurable Systems
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FPGA
1995
ACM
118views FPGA» more  FPGA 1995»
13 years 11 months ago
An SBus Monitor Board
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...
H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask
EDOC
2006
IEEE
14 years 1 months ago
Net-Centric Information Management
Information sharing is a key tenet of network-centric warfare (NCW). Information sharing succeeds when the right information is provided to the right people at the right time and ...
Scott Renner
JSA
2006
67views more  JSA 2006»
13 years 7 months ago
Speedup of NULL convention digital circuits using NULL cycle reduction
A NULL Cycle Reduction (NCR) technique is developed to increase the throughput of NULL Convention Logic systems, by reducing the time required to flush complete DATA wavefronts, c...
S. C. Smith
IEEEPACT
2005
IEEE
14 years 1 months ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
HICSS
2010
IEEE
185views Biometrics» more  HICSS 2010»
14 years 2 months ago
Concurrent Architecture for Automated Malware Classification
This paper introduces a new architecture for automating the generalization of program structure and the recognition of common patterns in the area of malware analysis. By using ma...
Timothy Daly, Luanne Burns