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» Parallel Processing Architectures for Reconfigurable Systems
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FPL
2009
Springer
113views Hardware» more  FPL 2009»
14 years 9 days ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...
FCCM
1999
IEEE
127views VLSI» more  FCCM 1999»
14 years 41 min ago
Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-Based Reconfigurable Hardwa
A significant obstacle to the widespread adoption of FPGAbased configurable computing hardware has been the difficulty of mapping applications onto this hardware. We are developin...
Benjamin A. Levine, Senthil Natarajan, Chandra Tan...
CORR
2010
Springer
198views Education» more  CORR 2010»
13 years 7 months ago
Space and the Synchronic A-Ram
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
Alexander Victor Berka
JRTIP
2008
249views more  JRTIP 2008»
13 years 7 months ago
Model-based mapping of reconfigurable image registration on FPGA platforms
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
Mainak Sen, Yashwanth Hemaraj, William Plishker, R...
ICRA
2002
IEEE
86views Robotics» more  ICRA 2002»
14 years 19 days ago
Optimized Binary Modular Reconfigurable Robotic Devices
—Binary robotic devices with large degrees of freedom have been proposed by a number of researchers. However, experimental implementations of these concepts have been built with ...
Moustapha Hafez, Matthew D. Lichter, Steven Dubows...