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» Parallel Processing Architectures for Reconfigurable Systems
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DSN
2007
IEEE
14 years 3 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
POLICY
2004
Springer
14 years 2 months ago
Policy-Based Mobile Ad Hoc Network Management
Ad hoc networking is the basis of the future military network-centric warfare architecture. Such networks are highly dynamic in nature, as mobile ad hoc networks are formed over w...
Ritu Chadha, Hong Cheng, Yuu-Heng Cheng, Cho-Yu Ja...
MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
13 years 7 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
WSC
1998
13 years 10 months ago
Parallel Implementation of a Molecular Dynamics Simulation Program
We have taken a NIST molecular dynamics simulation program (md3), which was configured as a single sequential process running on a CRAY C90 vector supercomputer, and parallelized ...
Alan Mink, Christophe Bailly
ICA3PP
2005
Springer
14 years 2 months ago
GridMD: Program Architecture for Distributed Molecular Simulation
In the present work we describe architectural concepts of the distributed molecular simulation package GridMD. The main purpose of this work is to underline the construction patter...
Ilya Valuev