1075 search results - page 150 / 215 » Parallel Programming with Transactional Memory |
124
Voted
SPAA
2010
ACM
15 years 7 months ago
2010
ACM
TL2 and similar STM algorithms deliver high scalability based on write-locking and invisible readers. In fact, no modern STM design locks to read along its common execution path b...
131
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DTJ
1998
15 years 2 months ago
1998
ir increasing use of abstraction, modularity, delayed binding, polymorphism, and source reuse, especially when these attributes are used in combination. Modern processor architectu...
135
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NOCS
2007
IEEE
15 years 8 months ago
2007
IEEE
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
120
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EMSOFT
2007
Springer
15 years 6 months ago
2007
Springer
The soundness of device drivers generally cannot be verified in isolation, but has to take into account the reactions of the hardware devices. In critical embedded systems, interf...
109
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SC
1995
ACM
15 years 5 months ago
1995
ACM
: Data distribution is one of the key aspects that a parallelizing compiler for a distributed memory architecture should consider, in order to get efficiency from the system. The ...