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DDECS
2006
IEEE
140views Hardware» more  DDECS 2006»
14 years 2 months ago
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming
Abstract-- Genetic Parallel Programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intende...
Zbysek Gajda
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
14 years 3 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
WSC
2008
14 years 1 months ago
A flexible and scalable experimentation layer
Modeling and simulation frameworks for use in different application domains, throughout the complete development process, and in different hardware environments need to be highly ...
Jan Himmelspach, Roland Ewald, Adelinde M. Uhrmach...
ICS
2009
Tsinghua U.
14 years 5 months ago
Dynamic topology aware load balancing algorithms for molecular dynamics applications
Molecular Dynamics applications enhance our understanding of biological phenomena through bio-molecular simulations. Large-scale parallelization of MD simulations is challenging b...
Abhinav Bhatele, Laxmikant V. Kalé, Sameer ...
HPCA
2012
IEEE
12 years 6 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...