287 search results - page 21 / 58 » Parallel Skyline Computation on Multicore Architectures |
IPPS
2010
IEEE
13 years 5 months ago
2010
IEEE
It is possible to implement the parallel random access machine (PRAM) on a chip multiprocessor (CMP) efficiently with an emulated shared memory (ESM) architecture to gain easy par...
JPDC
2010
13 years 2 months ago
2010
We show a method for parallelizing top down dynamic programs in a straightforward way by a careful choice of a lock-free shared hash table implementation and randomization of the ...
ICPP
2007
IEEE
14 years 2 months ago
2007
IEEE
As multi-core microprocessors are becoming widely adopted, the need to extract thread-level parallelism (TLP) from single-threaded applications in a seamless fashion increases. In...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires ...
SBACPAD
2008
IEEE
14 years 2 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...