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IPPS
2010
IEEE
13 years 5 months ago
A lock-free, cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring
Line-rate data traffic monitoring in high-speed networks is essential for network management. To satisfy the line-rate requirement, one can leverage multi-core architectures to par...
Patrick P. C. Lee, Tian Bu, Girish P. Chandranmeno...
ICS
2007
Tsinghua U.
14 years 1 months ago
Scheduling FFT computation on SMP and multicore systems
Increased complexity of memory systems to ameliorate the gap between the speed of processors and memory has made it increasingly harder for compilers to optimize an arbitrary code...
Ayaz Ali, S. Lennart Johnsson, Jaspal Subhlok
ATVA
2011
Springer
295views Hardware» more  ATVA 2011»
12 years 7 months ago
Parallel Nested Depth-First Searches for LTL Model Checking
Even though the well-known nested-depth first search algorithm for LTL model checking provides good performance, it cannot benefit from the recent advent of multi-core computers....
Sami Evangelista, Laure Petrucci, Samir Youcef
ICCS
2009
Springer
14 years 2 months ago
A Massively Parallel Architecture for Bioinformatics
Abstract. Today’s general purpose computers lack in meeting the requirements on computing performance for standard applications in bioinformatics like DNA sequence alignment, err...
Gerd Pfeiffer, Stefan Baumgart, Jan Schröder,...
NPC
2010
Springer
13 years 6 months ago
Exposing Tunable Parameters in Multi-threaded Numerical Code
Achieving high performance on today’s architectures requires careful orchestration of many optimization parameters. In particular, the presence of shared-caches on multicore arch...
Apan Qasem, Jichi Guo, Faizur Rahman, Qing Yi