Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
1 One common assumption of the existing models of load balancing is that the weights of resources and I/O buffer size are statically configured. Though the static configuration ...
Xiao Qin, Hong Jiang, Yifeng Zhu, David R. Swanson
We describe a programming framework for high performance clusters with various hardware accelerators. In this framework, users can utilize the available heterogeneous resources pr...
Kuen Hung Tsoi, Anson H. T. Tse, Peter Pietzuch, W...
It is now well established that the device scaling predicted by Moore’s Law is no longer a viable option for increasing the clock frequency of future uniprocessor systems at the...
Philippe Charles, Christian Grothoff, Vijay A. Sar...
Improving memory performance at software level is more effective in reducing the rapidly expanding gap between processor and memory performance. Loop transformations (e.g. loop un...
Surendra Byna, Xian-He Sun, William Gropp, Rajeev ...