Sciweavers

224 search results - page 42 / 45
» Parallel Switching in Connection-Oriented Networks
Sort
View
IEEEPACT
2008
IEEE
14 years 1 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
IPPS
2008
IEEE
14 years 1 months ago
LiteLoad: Content unaware routing for localizing P2P protocols
In today’s extensive worldwide Internet traffic, some 60% of network congestion is caused by Peer to Peer sessions. Consequently ISPs are facing many challenges like: paying fo...
Shay Horovitz, Danny Dolev
ACSC
2003
IEEE
14 years 20 days ago
Communication Performance Issues for Two Cluster Computers
Clusters of commodity machines have become a popular way of building cheap high performance parallel computers. Many of these designs rely on standard Ethernet networks as a syste...
Francis Vaughan, Duncan A. Grove, Paul D. Coddingt...
SPAA
1996
ACM
13 years 11 months ago
From AAPC Algorithms to High Performance Permutation Routing and Sorting
Several recent papers have proposed or analyzed optimal algorithms to route all-to-all personalizedcommunication (AAPC) over communication networks such as meshes, hypercubes and ...
Thomas Stricker, Jonathan C. Hardwick
HPDC
2009
IEEE
14 years 2 months ago
Interconnect agnostic checkpoint/restart in open MPI
Long running High Performance Computing (HPC) applications at scale must be able to tolerate inevitable faults if they are to harness current and future HPC systems. Message Passi...
Joshua Hursey, Timothy Mattox, Andrew Lumsdaine